1. Field of the Invention
Embodiments discussed herein related to a method of manufacturing a silicon carbide semiconductor device and silicon carbide semiconductor device that use a silicon carbide substrate.
2. Description of the Related Art
Semiconductor devices that use silicon carbide (SiC) as a material are expected as next generation semiconductor devices of silicon (Si). Compared to conventional semiconductor devices using Si as a material, SiC semiconductor devices have various advantages such as reducing device resistivity in the ON state to several hundredths and use in environments of high temperatures (200 degrees C. or greater). Such advantages are enabled by characteristics of the material itself such as the bandgap of SiC being about 3 times that of Si and the dielectric breakdown field strength being nearly 10 times that of Si.
Schottky barrier diodes (SBD), planar vertical metal oxide semiconductor field effect transistors (MOSFET) have become commercial SiC semiconductor devices. Nonetheless, a SiC MOSFET has a problem related to the gate oxide film/SiC interface, has low channel mobility, high device resistivity, and the capability of SiC is underutilized.
In recent years, SiC MOSFETs having low device resistivity and significantly improved channel mobility have been proposed accompanying improved oxidation and post oxidation annealing techniques called post oxidation anneal (POA).
Nonetheless, many problems remain with SiC MOSFETs, such as the instability of threshold voltage. When negative voltage is continuously applied to a gate of a MOSFET under high temperature, a problem occurs in that the threshold voltage drops to 0V or less and a normally off MOSFET becomes normally on (for example, refer to Japanese Laid-Open Patent Publication No. 2011-082454).
Measurement by the inventors obtained results where threshold voltage is +3V before voltage is applied and after voltage of −20V is applied for 10 minutes at 200 degrees C., the threshold voltage decreases to −12V. This is drop is the above problem of the gate oxide film/SiC interface and is thought to be caused by the interface state of a SiC interface being hundreds to thousands times greater than that of a Si interface.
Although the interface state is mainly a SiC dangling bond, to lower the interface state, gate oxide film formation at the SiC MOSFET by annealing in a NO gas or N2O gas atmosphere including nitrogen after gate oxidation has become mainstream recently.
Based on SIMS analysis, when annealing is performed in such atmospheres, the nitrogen clearly localizes in the interface. In this case, since the nitrogen enters a network with a structure of N≡(3 coordinates) and is stable, dangling bonds and the like are terminated, which is thought to be highly effective in lowering the interface state.
Nonetheless, nitrogen of a N≡(3 coordinates) structure takes on positive charge according to the reaction expressed by formula (1-1), when active hydrogen and holes are present nearby.:N≡(3 coordinates)+H+h(holes)→NH+≡(4 coordinates)+e−   (1-1)
When negative voltage is applied to the gate, since holes on an order of 1020 cm−3 are present at the gate oxide film/SiC interface, the reaction according to formula (1-1) occurs immediately when active hydrogen is present. When the temperature is high, NH+≡(4 coordinates) can penetrate to a position away from the interface where the NH+ becomes fixed, forming a hole trap near the interface.
When positive charge is condensed, in a p-type SiC surface, which is a channel of an n-type MOSFET, electrons collect whereby the surface concentration decreases and in a worst case, the surface transitions to n, the threshold voltage of the n-type MOSFET becomes negative, and the MOSFET exhibits a normally on characteristic.
As described, a SiC n-type MOSFET has a problem in that when negative voltage is continuously applied to the gate of a MOSFET at a high temperature, the threshold voltage decreases.